The invention relates to methods and apparatuses for generating a random sequence of commands and a random pattern, respectively, for simulation and/or test of a semiconductor device, in one embodiment a memory device.
Semiconductor devices, e.g., integrated (analog or digital) computing circuits, semiconductor memory devices such as functional memory devices (PLAs, PALs, etc.) and table memory devices (e.g., ROMs or RAMs, in one embodiment SRAMs and DRAMs), etc. are subject to comprehensive tests in the course of their manufacturing process.
When testing semiconductor devices, “DC tests” and/or “AC tests” may, for instance, be used as test methods.
In a DC test, a voltage (or current) of particular, especially constant, intensity may, for instance, be applied to a connection of a semiconductor device to be tested, and then the intensity of resulting currents (or voltages) may be measured, in one embodiment it may be examined whether these currents (or voltages) range within predetermined, desired threshold values.
Contrary to this, in an AC test, voltages (or currents), varying in intensity, may, for instance, be applied to connections of a semiconductor device, in one embodiment test pattern signals (“patterns”) by using which appropriate function tests may be performed at the respective semiconductor device.
Conventional function tests often use fault models for generating an appropriate test pattern. A fault model is a mathematical description of how a defect alters design behavior. A fault is said to be detected by a test pattern if, when applying the pattern to the design, any logic value observed at one or more of the circuit's primary outputs differs between the original design and the design with the fault. The pattern generating process for a targeted fault consists of two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.
Fault models are widely applied in tests of fully logic semiconductor devices, such as microprocessors, for example. However, fault models can not be used for full-chip simulation and test of e.g., memory devices, in one embodiment SDRAMs (Synchronous Dynamic Random Access Memory), due to, for example, the mixture between full-custom blocks, manually designed blocks, the memory array and usage of asynchronous timings on a SDRAM.
One approach to test these memory devices is to program a test particularly adapted to the respective memory device. However, this method is very time-consuming and costly.
For these and other reasons, there is a need for the present invention.